1. Field of the Invention
The invention relates to the field of semiconductor memory arrays, and in particular to reducing the semiconductor area of a wordline decoder.
2. Description of the Related Art
A prior art circuit for a local wordline decoder is shown in FIG. 1. Referring now to FIG. 1, P-channel transistor 101 (P1) and n-channel transistor 102 (N1) are connected in series between wordline driver input 107 (wldr) and a reference potential 109. Input 104 (mwln0) connects to the gates of transistor 101 and 102. Output 106 (lwl0) is connected to the junction of transistors 101 and 102. Drain and source of n-channel transistor 103 (N11) are connected between output 106 and reference potential 109, respectively. The gate of transistor 103 is connected to input 108 (wldrn), which is the inverse of input 107.
Referring now to FIG. 2, we show the input and output signals of the circuit of FIG. 1. Curve 21 represents input mwln0 (104) swinging from v.sub.h to logical zero during period t.sub.3. Curves 22 and 23 depict wordline driver inputs wldr 107 and wldrn 108 respectively. Curves 22 and 23 are shown to rise/fall t.sub.1 time before, and t.sub.2 time after period t.sub.3. t.sub.1 and t.sub.2 are guard zones around t.sub.3 to insure against unavoidable skew in the rise and fall of all three input signals. Curve 24 represents the local wordline decoder output lwl 106 and is shown selected during period t.sub.3, having swung from logical zero to v.sub.h.
U.S. Pat. No. 5,446,698 (McClure) discloses a redundant global wordline for local wordlines, however, the details of the local wordline decoder are not discussed. U.S. Pat. No. 5,587,960 (Ferris) describes a semiconductor memory with sub-wordlines but does not describe the details of the sub-wordline decoder. U.S Pat. No. 5,555,529 (Hose, Jr. et al) describes the use of a wordline decoder between a global wordline and a pair of even/odd wordlines, but the details of the wordline decoder are not disclosed.